The present invention relates to improvements in a pattern detector in an exposure system such as a reduction projection aligner system for use in processes for producing semiconductor integrated circuits, the pattern detector being well suited to precise positional measurements for the positioning of wafers, masks etc.
FIG. 1 shows an example of a prior-art pattern detector used in a reduction projection aligner system (refer to U.S. Pat. No. 4,380,395). In the reduction projection aligner system, a reticle 2 which is the original of a circuit pattern is illuminated by an illuminating optical system 1, to form a pattern on a wafer 4 through a reduction lens 3. At this time, the new pattern needs to be formed in conformity with the position of a pattern 5 which has been formed on the wafer 4 by the preceding step. The detection of a wafer position therefor has been effected by the following method. Using a light source 7 guided by an optical fiber or the like, a positioning pattern on the wafer 4 is illuminated through a reference pattern 6 on the reticle 2 and the reduction lens 3. Reflected light passes through a magnifying optical system 8 to be magnified and focused on the moving plane of a carriage 11 which has a slit 9. While the focusing plane is being scanned by the slit 9 so as to measure the movement value of this slit 9 by means of a linear encoder 12, the brightness of light passing through the slit is converted into an electric signal by a photomultiplier 10. FIG. 2 shows an example of the positioning pattern 15 of the wafer projected on the slit 9 (in the figure, numeral 14 indicates the scanning direction of the slit). Herein, when the photoelectric conversion output is taken on the axis of ordinates and the coordinate of the slit position on the axis of abscissas, a detection signal (derived signal) as shown in FIG. 3A is obtained.
In order to find the pattern position from the detection signal, there has heretofore been employed a method in which whether the symmetry of the detection signal is good or bad is decided by a processing circuit 13 (refer to the official gazette of Japanese Laid-open Patent Application No. 53-69063 corresponding to U.S. Pat. No. 4,115,762). More specifically, a function indicative of the degree of the symmetry as shown in FIG. 3B: ##EQU1## is evaluated by the use of a detection value X(I) obtained at a slit position I, and the position I at which the function becomes the minimum is deemed the pattern position. With this method, the detection signals X(I) for, e.g., 2500 points I are once stored in a memory, whereupon Equation (1) is calculated for the points I within a specified range by the use of a computer. The calculation of Equation (1) has the advantage of being less susceptible to the noise of the signal, but it has the disadvantage of requiring a long processing time because of a large number of operating steps. By way of example, when the resolution of the pattern detector is supposed to be 0.04 .mu.m as reckoned on the wafer and the calculation of Equation (1) is executed for the points I within a detection range of .+-.5 .mu.m by a minicomputer of the type ordinarily used (for example, "HITAC 10II", a product of Hitachi Ltd.), the processing time becomes about 0.7 second at m=200. However, a wider detection range is desired when the pattern detector is used in the reduction projection aligner system. In this regard, when the above method is applied to a detection range of .+-.15 .mu.m, the processing time becomes about 9 times longer, which becomes a factor for the degradation of the performance of the system. Especially in case of positioning each of a number of chips formed on the wafer, the long processing time forms a cause for lowering the wafer processing capability of the reduction projection aligner system. It has therefore been desired to shorten the processing time which is taken for the positional measurement.